Important message on the implementation of parasitic resistances in this
verilog-A release of PSP 102.2:

The addition of the parasitic resistor network to PSP implies that PSP 102.2 has five
internal nodes, leading to an increased simulation time and memory usage. Ideally, if
one or more resistance values are set to 0, the associated internal nodes are removed
from the model (node collapse).

Unfortunately, most verilog-A compilers do not yet (fully) support node-collapse. This
is NOT a limitation of this PSP 102.2 implementation, but is due to the fact that
most present day verilog-A compilers are not fully LRM 2.2 compliant and/or are
not sufficiently mature to fully optimize the generated model. As a result, using
this PSP verilog-A implementation directly in a circuit simulator may lead to one of
the following situations:

1. The code does not compile
2. The code compiles (with or without warnings). For each parasitic resistor one
internal node is created. However, nodes are not removed if one or more
resistance values is set to 0.
3. The code compiles (with or without warnings). For each parasitic resistor TWO
internal nodes are created. However, nodes are not removed if one or more
resistance values is set to 0.
4. The code compiles. For each parasitic resistor one internal node is created.
For some of the resistors, the associated internal node is removed if the
resistance value is set to 0, but not for all.
5. The code compiles. For each parasitic resistor an internal node is created.
For each of the resistors, the associated internal node is removed if the
resistance value is set to 0.

Obviously, situation 5 is the intended behavior.

For convenience of the user, an alternative verilog-A implementation of PSP 102.2 is
provided, which should compile without problems in all present day verilog-A
compilers. Its usage is, however, limited to one of the following two situations.

(A) All five parasitic resistors are set to a nonzero value.
(B) All five parasitic resistors are set to 0.

For case (A), this Verilog-A code can be compiled as is. Compared to the official
release, the difference is that all five parasitic resistance values default to 1e-3
not 0) and are clipped to a lower limit of 1e-6 (not 0). The resistors are never
removed from the topology.

For case (B), this Verilog-A code can be compiled after commenting or removing the line

`define Rnetwork

in the .va-file. Then, the parasitic resistors are completely removed from the topology
and the corresponding parameter values are simply ignored.